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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Low Skew CMOS PLL Clock Driver
With Power-Down/Power-Up Feature
The MC88920 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family. The PLL allows the the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88920 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency.
MC88920
LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature
* 2X_Q Output Meets All Requirements of the 20 and 25MHz 68040
Microprocessor PCLK Input Specifications
* Three Outputs (Q0-Q2) With Output-Output Skew <500ps and Six
Outputs Total (Q0-Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase and Frequency Locked to the SYNC Input
20 1
* The Phase Variation From Part-to-Part Between SYNC and the `Q'
Outputs Is Less Than 600ps (Derived From the TPD Specification, Which Defines the Part-to-Part Skew)
* SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4 * Additional Outputs Available at 2X and /2 the System `Q' Frequency.
Also a Q (180 Phase Shift) Output Available.
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04
* All Outputs Have 36mA Drive (Equal High and Low) CMOS Levels. Can Drive Either CMOS or TTL Inputs. All Inputs Are
TTL-Level Compatible
* Test Mode Pin (PLL_EN) Provided for Low Frequency Testing * Special Power-Down Mode With 2X_Q, Q0, and Q1 Being Reset (With MR), and Other Outputs Remain Running. 2X_Q, Q0
and Q1 Are Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated Three `Q' outputs (Q0-Q2) are provided with less than 500ps skew between their rising edges. The Q3 output is inverted (180 phase shift) from the `Q' outputs. A 2X_Q output runs at twice the `Q' output frequency. The 2X_Q output is ideal for 68040 systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 20 and 25MHz 68040. The Q/2 output runs at 1/2 the `Q' frequency. This output is fed back internally, providing a fixed 2X multiplication from the `Q' outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided) the input/output frequency relationships are fixed. In normal phase-locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88920 in a static `test mode'. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The RST_OUT(LOCK) pin doubles as a phase-lock indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until phase-lock is achieved. When phase-lock occurs, the RST_OUT(LOCK) is released and a pull-up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT(LOCK) pin will stay low for 1024 cycles of the `Q' output frequency after the RST_IN pin is brought back high. Description of the RST_IN/RST_OUT(LOCK) Functionality The RST_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system power-up, the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 `Q' output cycles after phase-lock is achieved the RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull-up resistor (see the AC/DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power-up, the RST_OUT(LOCK) pin will remain low.
8/95
(c) Motorola, Inc. 1995
1
REV 2
MC88920
Q3 VCC
1 2 3 4 5 6 7 8 9
20 GND 19 2X_Q 18 Q/2 17 VCC 16 Q2 15 GND 14 RST_OUT(LOCK) 13 PLL_EN 12 Q1 11 VCC
Power-Down Mode Functionality The MC88920 has a special feature designed in to allow the processor clock inputs to be reset for total processor power-down, and then to return to phase-locked operation very quickly when the processor is powered-up again. The MR pin resets outputs 2X_Q, Q0 and Q1 only leaving the other outputs operational for other system activity. When MR is negated, all outputs will be operating normally within 3 clock cycles.
MR RST_IN VCC(AN) RC1 GND(AN) SYNC GND
Q0 10
Pinout: 20-Lead Wide SOIC Package (Top View)
Description of the RST_IN/RST_OUT(LOCK) Functionality (continued) After the system start-up is complete and the 88920 is phase-locked to the SYNC input signal (RST_OUT high), the processor reset functionality can be utilized. When the RST_IN pin is toggled low (min. pulse width=10nS), RST_OUT(LOCK) will go to the low state and remain there for 1024 cycles of the `Q' output frequency (512 SYNC cycles). During the time in which the RST_OUT(LOCK) is actively pulled low, all the 88920 clock outputs will continue operating correctly and in a locked condition to the SYNC input (clock signals to the 68030/040 family of processors must continue while the processor is in reset). A propagation delay after the 1024th cycle RST_OUT(LOCK) goes back to the high impedance state to be pulled high by the resistor. phase-lock to the reference source, some constraints must be placed on the power supply ramp rate to make sure the RST_OUT(LOCK) signal holds the processor in reset during system start-up (power-up). With the recommended loop filter values (see Figure 7) the lock time is approximately 10ms. The phase-lock loop will begin attempting to lock to a reference source (if it is present) when VCC reaches 2V. If the VCC ramp rate is significantly slower than 10ms, then the PLL could lock to the reference source, causing RST_OUT(LOCK) to go high before the 88920 and '030/040 processor is fully powered up, violating the processor reset specification. Therefore, if it is necessary for the RST_IN pin to be held high during power-up, the VCC ramp rate must be less than 10mS for proper `030/040 reset operation. This ramp rate restriction can be ignored if the RST_IN pin can be held low during system start-up (which holds RST_OUT low). The RST_OUT(LOCK) pin will then be pulled back high 1024 cycles after the RST_IN pin goes high.
Power Supply Ramp Rate Restriction for Correct 030/040 Processor Reset Operation During System Start-up
Because the RST_OUT(LOCK) pin is an indicator of CAPACITANCE AND POWER SPECIFICATIONS
Symbol CIN CPD PD1 PD2 Parameter Input Capacitance Power Dissipation Capacitance Power Dissipation at 33MHz With 50 Thevenin Termination Power Dissipation at 33MHz With 50 Parallel Termination to GND
Value Typ 4.5 40 15mW/Output 90mW/Device 37.5mW/Output 225mW/Device
Unit pF pF mW mW
Test Conditions VCC = 5.0V VCC = 5.0V VCC = 5.0V T = 25C VCC = 5.0V T = 25C
MOTOROLA
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TIMING SOLUTIONS BR1333 -- REV 5
MC88920
MAXIMUM RATINGS*
Symbol VCC, AVCC Vin Vout Iin Iout ICC Tstg Parameter DC Supply Voltage Referenced to GND DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, Per Pin DC Output Sink/Source Current, Per Pin DC VCC or GND Current Per Output Pin Storage Temperature Limits -0.5 to 7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 -65 to +150 Unit V V V mA mA mA C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Vout TA ESD Supply Voltage DC Input Voltage DC Output Voltage Ambient Operating Temperature Static Discharge Voltage Parameter Limits 5.0 10% 0 to VCC 0 to VCC 0 to 70 > 1500 Unit V V V C V
DC CHARACTERISTICS (TA = 0C to 70C; VCC = 5.0V 5%)
Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Minimum Low Level Input Voltage Minimum High Level Output Voltage VCC 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 5.25 5.25 5.25 5.25 Maximum Quiescent Supply Current 5.25 Guaranteed Limits 2.0 2.0 0.8 0.8 4.01 4.51 0.44 0.44 1.0 2.0 2 88 -88 750 Unit V V V Condition VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V VIN = VIH or VIL IOH -36mA -36mA VIN = VIH or VIL IOH +36mA1 +36mA VI = VCC, GND VI = VCC - 2.1V VOLD = 1.0V Max VOHD = 3.85 Min VI = VCC, GND
VOL
Minimum Low Level Output Voltage
V
IIN ICCT IOLD IOHD ICC 1. 2. 3.
Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic3 Output Current
A mA mA mA A
IOL is +12mA for the RST_OUT output. The PLL_EN input pin is not guaranteed to meet this specification. Maximum test duration 2.0ms, one output loaded at a time.
TIMING SOLUTIONS BR1333 -- REV 5
3
MOTOROLA
MC88920
RST_OUT
RST_IN
LOCK INDICATOR AND RESET_OUT 1024 CYCLE COUNT CIRCUITRY RC1 D R VCO D R Q Q1 Q Q0
2X_Q
SYNC1 PFD
CH PUMP
PLL_EN
0 POWER-ON RESET
1 D /2 R Q Q2
D MR R
Q Q
"Dummy" Flip-Flop to Maintain Phase-Locked Operation
D R
Q
Q3
D R
Q
Q/2
Figure 1. MC88920 Logic Block Diagram SYNC INPUT TIMING REQUIREMENTS
Symbol tRISE/FALL SYNC Input tCYCLE, SYNC Input Duty Cycle Rise/Fall Time, SYNC Input From 0.8V to 2.0V Input Clock Period SYNC Input Duty Cycle, SYNC Input Parameter Minimum -- 1 f2X_Q 4 50% 25% Maximum 5.0 200 Unit ns ns
FREQUENCY SPECIFICATIONS (TA = 0C to 70C; VCC = 5.0V 5%)
Symbol Fmax (2X_Q) Fmax (`Q') Parameter Maximum Operating Frequency, 2X_Q Output Maximum Operating Frequency, Q0-Q2, Q3 Outputs Guaranteed Minimum 50 25 Unit MHz MHz
1. Maximum Operating Frequency is guaranteed with the 88920 in a phase-locked condition, and all outputs loaded at 50pF.
MOTOROLA
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TIMING SOLUTIONS BR1333 -- REV 5
MC88920
AC CHARACTERISTICS (TA = 0C to 70C; VCC = 5.0V 5%)
Symbol tRISE/FALL1 All Outputs tRISE/FALL1 2X_Q Output tpulse width(a)1 (Q0, Q1, Q2, Q3) tpulse width(b)1 (2X_Q Output) tPD1,4 SYNC - Q/2 Parameter Rise/Fall Time, All Outputs into 50 Load Rise/Fall Time into a 20pF Load, With Termination Specified in AppNote 3 Output Pulse Width Q0, Q1, Q2, Q3 at VCC/2 Output Pulse Width 2X_Q at VCC/2 SYNC Input to Q/2 Output Delay (Measured at SYNC and Q/2 Pins) Mimimum 0.3 0.5 0.5tcycle - 0.55 Maximum 1.6 1.6 0.5tcycle + 0.55 Unit ns ns ns Condition tRISE - 0.8V to 2.0V tFALL - 2.0V to 0.8V tRISE - 0.8V to 2.0V tFALL - 2.0V to 0.8V 50 Load Terminated to VCC/2 (See Application Note 3) 50 Load Terminated to VCC/2 (See Application Note 3) With 1M From RC1 to An VCC (See Application Note 2) With 1M From RC1 to An GND (See Application Note 2) Into a 50 Load Terminated to VCC/2 (See Timing Diagram in Figure 6) Into a 50 Load Terminated to VCC/2 (See Timing Diagram in Figure 6) Into a 50 Load Terminated to VCC/2 (See Timing Diagram in Figure 6)
0.5tcycle - 0.55
0.5tcycle + 0.55
ns
-0.75
-0.15
ns
+1.25 7
+3.25 7
ns
tSKEWr1,2 (Rising)
Output-to-Output Skew Between Outputs Q0-Q2, Q/2 (Rising Edge Only) Output-to-Output Skew Between Outputs Q0-Q2 (Falling Edge Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q2 Rising Q3 Falling Phase-Lock Acquisition Time, All Outputs to SYNC Input Propagation Delay, MR to Any Output (High-Low) Reset Recovery Time rising MR edge to falling SYNC edge Recovery Time for Outputs 2X_Q, Q0, Q1 to Return to Normal PLL Operation Minimum Pulse Width, MR input Low Minimum Pulse Width, RST_IN Low Output Enable Time RST_IN Low to RST_OUT Low Output Enable Time RST_IN High to RST_OUT High Z
--
500
ps
tSKEWf1,2 (Falling)
--
1.0
ns
tSKEWall1,2
--
1.0
ns
tLOCK3 tPHL MR - Q tREC, MR to SYNC6 tREC, MR to Normal Operation tW, MR LOW6 tW, RST_IN LOW tPZL tPLZ
1 1.5 9 -- 5 10 1.5 1016 `Q' Cycles (508 Q/2 Cycles)
10 13.5 -- 3 Clock Cycles (Q Frequency) -- -- 16.5 1024 `Q' Cycles (512 Q/2 Cycles)
ms ns ns ns ns ns ns ns When in Phase-Lock See Application Note 5 See Application Note 5 Into a 50 Load Terminated to VCC/2
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this methodology. 2. Under equally loaded conditions and at a fixed temperature and voltage. 3. With VCC fully powered-on: tCLOCK Max is with C1 = 0.1F; tLOCK Min is with C1 = 0.01F. 4. See Application Note 4 for the distribution in time of each output referenced to SYNC. 5. Refer to Application Note 3 to translate signals to a 1.5V threshold. 6. Specification is valid only when the PLL_EN pin is low. 7. This is a typical specification only, worst case guarantees are not provided.
TIMING SOLUTIONS BR1333 -- REV 5
5
MOTOROLA
MC88920
Application Notes
1. Several specifications can only be measured when the MC88920 is in phase-locked operation. It is not possible to have the part in phase-lock on ATE (automated test equipment). Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88920 units were fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. IC performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area. IC performance to each specification and fab variation were used to set performance limits of ATE testable specifications within those which are to be guaranteed by statistical characterization. In this way, all units passing the ATE test will meet or exceed the non-tested specifications limits. 2. A 1M resistor tied to either Analog VCC or Analog GND, as shown in Figure 2, is required to ensure no jitter is present on the MC88920 outputs. This technique causes a phase offset between the SYNC input and the Q0 output, measured at the pins. The tPD spec describes how this offset varies with process, temperature, and voltage. The specs were arrived at by measuring the phase relationship for the 14 lots described in note 1 while the part was in phase-locked operation. The actual measurements were made with a 10MHz SYNC input (1.0ns edge rate from 0.8V to 2.0V). The phase measurements were made at 1.5V. See Figure 2 for a graphical description. 3. Two specs (tRISE/FALL and tPULSE Width 2X_Q output, see AC Specifications) guarantee that the MC88920 meets the 20MHz and 25MHz 68040 P-Clock input specification (at 40MHz and 50MHz). For these two specs to be guaranteed by Motorola, the termination scheme shown in Figure 3 must be used. For applications which require 1.5V thresholds, but do not require a tight duty cycle the RP resistor can be ignored. 4. The tPD spec (SYNC to Q/2) guarantees how close the Q/2 output will be locked to the reference input connected to the SYNC input (including temperature and voltage variation). This also tells what the skew from the Q/2 output on one part connected to a given reference input, to the Q/2 output on one or more parts connected to that reference input (assuming equal delay from the referenceinput to the SYNC input of each part). Therefore the tPD spec is equivalent to a part-to-part specification. However, to correctly predict the skew from a given output on one part to any other output on one or more other parts, the distribution of each output in relation to the SYNC input must be known. This distribution for the MC88920 is provided in Table 1. TABLE 1. Distribution of Each Output versus SYNC
Output 2X_Q Q0 Q1 Q2 Q3 Q/2 -(ps) TBD TBD TBD TBD TBD TBD +(ps) TBD TBD TBD TBD TBD TBD
RC1 EXTERNAL LOOP FILTER
ANALOG VCC 1M REFERENCE RESISTOR
RC1 R2 C1
330 0.1F
R2 C1 1M REFERENCE RESISTOR
330 0.1F
ANALOG GND WITH THE 1M RESISTOR TIED IN THIS FASHION THE TPD SPECIFICATION, MEASURED AT THE INPUT PINS IS: tPD = 2.25ns 1.0ns (TYPICAL VALUES) 3V SYNC INPUT 2.25ns OFFSET Q0 OUTPUT 5V Q0 OUTPUT SYNC INPUT
ANALOG GND WITH THE 1M RESISTOR TIED IN THIS FASHION THE TPD SPECIFICATION, MEASURED AT THE INPUT PINS IS: tPD = -0.80ns 0.30ns 3V -0.8ns OFFSET 5V
Figure 2. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present When a 1M Resistor Is Tied to VCC or Ground
MOTOROLA
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TIMING SOLUTIONS BR1333 -- REV 5
MC88920
Zo (CLOCK TRACE) RP
88920 2X_Q OUTPUT
Rs
Rs = Zo - 7
68040 P-CLOC K INPUT RP = 1.5Zo
Figure 3. MC68040 P-Clock Input Termination Scheme
RST_OUT PIN 1K INTERNAL LOGIC CL
VCC
12.5MHz CRYSTAL OSCILLATOR
2X_Q SYNC Q0 Q1 Q2 Q3 Q/2 RST_OUT
50MHz P-CLOCK OUTPUT 25MHz B-CLOCK AND SYSTEM OUTPUTS
MR PLL_EN RST_IN
ANALOG GND
Figure 4. RST_OUT Test Circuit
Figure 5. Logical Representation of the MC88920 With Input/Output Frequency Relationships
SYNC Input tCYCLE SYNC Input tSKEWall tSKEWf tSKEWr tSKEWf tSKEWr
Q0-Q2 Outputs tCYCLE `Q' Outputs Q3 Output
2X_Q Output
Q/2 Output
Figure 6. Output/Input Switching Waveforms and Timing Relationships
Timing Notes
1. The MC88920 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as `windows', not as a deviation around a center point.
TIMING SOLUTIONS BR1333 -- REV 5
7
MOTOROLA
MC88920
The tPD spec includes the full temperature range from 0C to 70C and the full VCC range from 4.75V to 5.25V. If the T and VCC is a given system are less than the specification limits, the tPD spec window will be reduced. The tPD window for a given T and VCC is given by the following regression formula: TBD 5. The RST_OUT pin is an open drain N-Channel output. Therefore an external pull-up resistor must be provide to pull up the RST_OUT pin when it goes into the high impedance state (after the MC88920 is phase-locked to the reference input with RST_IN held high or 1024 `Q' cycles after the RST_IN pin goes high when the part is locked). In the tPLZ and tPZL specifications, a 1K resistor is used as a pull-up as shown in Figure 4.
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 7 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: 1a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin. 1b. The 47 resistors, the 10F low frequency bypass capacitor, and the 0.1F high frequency bypass capacitor form a wide bandwidth filter that will make the 88920 PLL insensitive to voltage transients from the system digital VCC supply and ground planes. This filter will typically ensure that a 100mV step deviation on the digital VCC supply will cause no more than a 100ps phase deviation on the 88920 outputs. A 250mV step deviation on VCC using the recommended filter values will cause no more than a 250ps phase deviation; if a 25F bypass capacitor is used (instead of 10F) a 250mV VCC step will cause no more than a 100ps phase deviation. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, the above described VCC step deviations should not occur at the 88920's digital VCC supply. The purpose of the bypass filtering scheme shown in Figure 7 is to give the 88920 additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1c. There are no special requirements set forth for the loop filter resistors (1M and 330). The loop filter capacitor (0.1uF) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 1d. The 1M reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead-band. If the VCO (2X_Q output) is running above 40MHz, the 1M resistor provides the correct amount of current injection into the charge pump (2-3A). 2. In addition to the bypass capacitors used in the analog filter of Figure 7, there should be a 0.1F bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88920 outputs, in addition to reducing potential for noise in the `analog' section of the chip. These bypass capacitors should also be tied as close to the 88920 package as possible.
BOARD VCC 47 5 1M 10F LOW FREQ BIAS 0.1F HIGH FREQ BIAS 0.1F (LOOP FILTER CAP) 7 47 330 6 RC1 ANALOG VCC ANALOG LOOP FILTER/VCO SECTION OF THE MC88920 20-PIN SOIC PACKAGE (NOT DRAWN TO SCALE)
ANALOG GND
BOARD GND
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES IS ALL THAT IS NECESSARY TO USE THE MC88920 IN A NORMAL DIGITAL ENVIRONMENT.
Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88920
MOTOROLA
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TIMING SOLUTIONS BR1333 -- REV 5
MC88920
MC68040 12.5MHz X-TAL OSCILLATOR 2X_Q SYNC Q0 Q1 Q2 RST_IN Q3 RST_OUT MEMORY MODULE 25MHz BCLK RESET 50MHz PCLK
ASIC
ASIC
SYSTEM RESET
Figure 8. Typical MC88920/MC68040 System Configuration
TIMING SOLUTIONS BR1333 -- REV 5
9
MOTOROLA
MC88920
OUTLINE DIMENSIONS
DW SUFFIX SOIC PACKAGE CASE 751D-03
-A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751D-01, AND -02 OBSOLETE, NEW STANDARD 751D-03. MILLIMETERS MIN MAX A 12.65 12.95 7.60 B 7.40 2.65 C 2.35 0.49 D 0.35 0.90 F 0.50 1.27 BSC G J 0.25 0.32 K 0.10 0.25 M 7 0 P 10.05 10.55 R 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029
-B1 10
P
10 PL
0.25 (0.010)
M
B
M
G
R X 45 C K
M
DIM
-T-
SEATING PLANE
M D 20 PL 0.25 (0.010) TB
S
F
J
A
S
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MOTOROLA
CODELINE
10
*MC88920/D*
MC88920/D TIMING SOLUTIONS BR1333 -- REV 5

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